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Global Mixed-mode Technology Inc.
G1428
2W Stereo Audio Amplifier
2X\6X\12X\24X Selectable Gain Settings
Features
Internal Gain Control, Which Eliminates External Gain-Setting Resistors Depop Circuitry Integrated Output Power at 1% THD+N, VDD=5V --2.0W/CH (typical) into a 4 Load --1.2W/CH (typical) into a 8 Load Bridge-Tied Load (BTL), Single-Ended (SE) Stereo Input MUX PC-Beep Input Fully differential Input Shutdown Control Available Surface-Mount Power Package 24-Pin TSSOP-P
General Description
G1428 is a stereo audio power amplifier in 24pin TSSOP thermal pad package. It can drive 2.0W continuous RMS power into 4 load per channel in Bridge-Tied Load (BTL) mode at 5V supply voltage. Its THD is smaller than 1% under the above operation condition. To simplify the audio system design in the notebook application, G1428 supports the Bridge-Tied Load (BTL) mode for driving the speakers, Single-End (SE) mode for driving the headphone. For the low current consumption applications, the SHDN mode is supported to disable G1428 when it is idle. The current consumption can be reduced to 160A (typically). Amplifier gain is internally configured and controlled by two terminals (GAIN0, GAIN1). BTL gain settings of 2, 6, 12, 24V/V are provided, while SE gain is always configured as 1V/V for headphone driving. G1428 also supports two input paths, that means two different amplitude AC signals can be applied and chosen by setting HP/ LINE pin. It enhances the hardware designing flexibility.
Applications
Stereo Power Amplifiers for Notebooks or Desktop Computers Multimedia Monitors Stereo Power Amplifiers for Portable Audio Systems
Ordering Information
ORDER NUMBER
G1428F31U Note: U: Tape & Reel (FD): Thermal Pad
ORDER NUMBER (Pb free)
G1428F31Uf
MARKING
G1428
TEMP. RANGE
-40C to +85C
PACKAGE
TSSOP-24 (FD)
Pin Configuration
GND/HS GAIN0 GAIN1 LOUT+ LLINEIN LPHIN PVDD RIN LOUT-
1 2 3 4 5 6 7 8 9
24 23 22 21 20 19 18 17 16 15 14 13
GND/HS RLINEIN SHUTDOWN ROUT+ RHPIN VDD PVDD HP/LINE ROUTSE/BTL PC-BEEP GND/HS 14
Thermal Pad
LIN 10 BYPASS 11 GND/HS 12
Top View TSSOP-24
Bottom View
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Absolute Maximum Ratings
Supply Voltage, VCC.............................................6V Operating Ambient Temperature Range TA...................................................-40C to +85C Maximum Junction Temperature, TJ...................150C Storage Temperature Range, TSTG.......-65C to+150C Reflow Temperature (soldering, 10sec)............260C
Note:
(1) (2)
G1428
Power Dissipation (1) TA 25C ................................................2.7W TA 70C ...............................................1.7W Electrostatic Discharge, VESD Human body mode......................................3000(2)
: Recommended PCB Layout : Human body model : C = 100pF, R = 1500, 3 positive pulses plus 3 negative pulses
Electrical Characteristics
DC Electrical Characteristics, TA=+25C PARAMETER
Supply voltage VDD High-Level Input voltage, VIH Low-Level Input voltage, VIL DC Differential Output Voltage Supply Current in Mute Mode IDD in Shutdown
SYMBOL
VDD VIH VIL VO(DIFF) IDD ISD
CONDITION
SE/ BTL , HP/ LINE , SHUTDOWN , GAIN0 , GAIN1 SE/ BTL , HP/ LINE , SHUTDOWN , GAIN0, GAIN1 VDD = 5V,Gain = 2 VDD = 5V VDD = 5V Stereo BTL Stereo SE
MIN
4.5 3.5 ---------
TYP
5 ----5 7.5 4 160
MAX
5.5 --1 50 13 7 300
UNIT
V V V mV mA A
(AC Operation Characteristics, VDD = 5.0V, TA=+25C, RL = 4, unless otherwise noted) PARAMETER SYMBOL CONDITION
THD = 1%, BTL, RL = 4 G=-2V/V THD = 1%, BTL, RL = 8 G=-2V/V THD = 10%, BTL, RL = 4 G=-2V/V THD = 10%, BTL, RL = 8 G=-2V/V THD = 0.1%, SE, RL = 32 PO = 1.6W, BTL, RL = 4 G=-2V/V Total harmonic distortion plus noise THD+N PO = 1W, BTL, RL = 8 G=-2V/V PO = 75mW, SE, RL = 32 VI = 1V, RL = 10K, SE THD = 5% F=1kHz, BTL mode G=-2V/V CBYP=1F f = 1kHz
MIN
-----------------------------
TYP
2 1.25 2.5 1.6 85 100 60 80 30 >15 68 80 80
MAX
---------------------------
UNIT
W
Output power (each channel) see Note
P(OUT)
mW
m%
Maximum output power bandwidth Power supply ripple rejection Channel-to-channel output separation Line/HP input separation BTL attenuation in SE mode Input impedance Signal-to-noise ratio Output noise voltage
BOM PSRR
kHz dB dB dB dB M dB V (rms)
ZI Vn PO = 500mW, BTL, G=-2V/V BTL, G=-2V/V, A Weighted filter
85 --See Table 2 --90 ----45 ---
Note :Output power is measured at the output terminals of the IC at 1kHz.
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Typical Characteristics
Table of Graphs
G1428
FIGURE
1,2,7,8,13,14,19,21 3,4,5,6,9,10,11,12,15,16,17,18,20 22 27 23,24 25,26 28,29 30,31
vs Frequency THD +N Total harmonic distortion plus noise Output noise voltage Vn PO PD Supply ripple rejection ratio Crosstalk Output power Power dissipation vs Output Power vs Output Voltage vs Frequency vs Frequency vs Frequency vs Load Resistance vs Output Power
Toal Harmonic Distortion Plus Noise vs Frequency
10 5 10
Toal Harmonic Distortion Plus Noise vs Frequency
5
2 1 0.5 % 0.2 0.1 0.05
VDD=5V RL=3 BTL Po=1.75W
2
VDD=5V RL=3 BTL,Av=-2V/V
Av=-24V/V
1 0.5 % 0.2
Po=1W
Po=0.5W
Av=-2V/V
0.1 0.05
0.02 0.01 20
Av=-6V/V
50 100 200
Av=-12V/V
5 00 Hz 1k 2k 5k 10k 20 k
0.02 0.01 20
Po=1.75W
50 100 20 0 5 00 Hz 1k 2k 5k 10k 20 k
Figure 1
Figure 2
Toal Harmonic Distortion Plus Noise vs Output Power
10 5 10
Toal Harmonic Distortion Plus Noise vs Output Power
5
15kHz
2 1 0.5 % 0.2 0.1 0.05
VDD=5V RL=3 BTL,Av=-2V/V
15kHz
2 1 0.5
1kHz
1kHz
% 0.2 0.1
20Hz
0.05
0.02 0.01 3m
0.02 0.01 3m
VDD=5V RL=3 BTL,Av=-6V/V
5m 10m 20m 50 m 100m W
20Hz
5m
10m
20m
50 m
100m W
200 m
50 0m
1
2
3
200m
50 0m
1
2
3
Figure 3
Figure 4
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G1428
Toal Harmonic Distortion Plus Noise vs Output Power
Toal Harmonic Distortion Plus Noise vs Output Power
10 5 10
15kHz
5
2 1 0.5 % 0.2 0.1 0.05
2 1
1kHz
15kHz
1kHz
%
0.5
0.2
20Hz VDD=5V RL=3 BTL,Av=-24V/V
VDD=5V RL=3 BTL,Av=-12V/V
20Hz
0.1 0.05
0.02 0.01 3m
0.02 0.01 3m
5m
10m
20m
50 m
100m W
200 m
50 0m
1
2
3
5m
10m
20m
50 m
100m W
200m
50 0m
1
2
3
Figure 5
Figure 6
Toal Harmonic Distortion Plus Noise vs Frequency
10 5 10 5
Toal Harmonic Distortion Plus Noise vs Frequency
Av=-24V/V
2 1 0.5 % 0.2 0.1 0.05
2 1 0.5
VDD=5V RL=4 BTL,Av=-2V/V Po=0.25W Po=1.5W
Av=-12V/V VDD=5V RL=4 BTL Po=1.75W
2k 5k 10k 20 k
% 0.2 0.1 0.05
0.02 0.01 20
Av=-2V/V
50 100 200
Av=-6V/V
5 00 Hz 1k
0.02 0.01 20
Po=1W
50 100 20 0 5 00 Hz 1k 2k 5k 10k 20 k
Figure 7
Figure 8
Toal Harmonic Distortion Plus Noise vs Output Power
10 5 10
Toal Harmonic Distortion Plus Noise vs Output Power
5
15kHz
2 1 0.5 % 0.2 0.1 0.05
VDD=5V RL=4 BTL,Av=-2V/V
15kHz
2 1 0.5 % 0.2 0.1 0.05
1kHz
1kHz
20Hz
0.02 0.01 3m
0.02 0.01 3m
VDD=5V RL=4 BTL,Av=-6V/V
5m 10m 20m 50 m 100m W 200m
20Hz
5m
10m
20m
50 m
100m W
200 m
50 0m
1
2
3
50 0m
1
2
3
Figure 9
Figure 10
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G1428
Toal Harmonic Distortion Plus Noise vs Output Power
Toal Harmonic Distortion Plus Noise vs Output Power
10 5 10
15kHz
5
15kHz 1kHz
2 1 0.5 % 0.2 0.1 0.05 %
2
1kHz
1 0.5
0.2
VDD=5V RL=4 BTL,Av=-12V/V
0.1
20Hz VDD=5V RL=4 BTL,Av=-24V/V
20Hz
0.05
0.02 0.01 3m
0.02 0.01 3m
5m
10m
20m
50 m
100m W
200 m
50 0m
1
2
3
5m
10m
20m
50 m
100m W
200 m
50 0m
1
2
3
Figure 11
Figure 12
Toal Harmonic Distortion Plus Noise vs Frequency
10 5 10
Toal Harmonic Distortion Plus Noise vs Frequency
5
2 1 0.5 % 0.2 0.1 0.05
VDD=5V RL=8 BTL,Av=-2V/V
2 1 0.5 %
VDD=5V RL=8 BTL Po=1W
Av=-24V/V
Av=-12V/V
0.2 0.1
Po=0.25W Po=1W Po=0.5W
50 100 20 0 5 00 Hz 1k 2k 5k 10k 20 k
0.05
Av=-2V/V Av=-6V/V
50 100 20 0 5 00 Hz 1k 2k 5k 10k 20 k
0.02 0.01 20
0.02 0.01 20
Figure 13
Figure 14
Toal Harmonic Distortion Plus Noise vs Output Power
10 5 10
Toal Harmonic Distortion Plus Noise vs Output Power
5
2 1 0.5 % 0.2 0.1 0.05
15kHz
VDD=5V RL=8 BTL,Av=-2V/V
15kHz
2 1 0.5 %
VDD=5V RL=8 BTL,Av=-6V/V
1kHz
1kHz
0.2 0.1 0.05
20Hz
0.02 0.01 3m
20Hz
5m 10m 20m 50 m 100m W 200 m 50 0m 1 2 3
0.02 0.01 3m
5m
10m
20m
50 m
100m W
200 m
50 0m
1
2
3
Figure 15
Figure 16
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G1428
Toal Harmonic Distortion Plus Noise vs Output Power
Toal Harmonic Distortion Plus Noise vs Output Power
10 5 10
15kHz
5
15kHz
2 1 0.5 % 0.2 0.1 0.05 %
2 1 0.5
1kHz
1kHz
0.2 0.1 0.05
VDD=5V RL=8 BTL,Av=-12V/V
5m 10m 20m 50m 100m W 200m
0.02 0.01 3m
20Hz
500m 1 2 3
VDD=5V RL=8 BTL,Av=-24V/V
20Hz
0.02 0.01 3m
5m
10m
20m
50m
100m W
200m
500m
1
2
3
Figure 17
Figure 18
Toal Harmonic Distortion Plus Noise vs Frequency
10 5 10
Toal Harmonic Distortion Plus Noise vs Output Power
5
2 1 0.5 % 0.2 0.1 0.05
VDD=5V RL=32 SE,Av=-1V/V
2 1 0.5
VDD=5V RL=32 SE,Av=-1V/V
Po=50mW
%
15kHz
Po=75mW
0.2 0.1 0.05
20Hz 1kHz
2m 5m 10m 20m W 50m 100m 200m 500m 1
0.02 0.01 20
Po=25mW
50 100 200 500 Hz 1k 2k 5k 10k 20k
0.02 0.01 1m
Figure 19
Figure 20
Toal Harmonic Distortion Plus Noise vs Frequency
10 5 10 5
Toal Harmonic Distortion Plus Noise vs Output Voltage
VDD=5V RL=10 SE,Av=-1V/V Cout=1000F
2 1 0.5 % 0.2 0.1 0.05
VDD=5V RL=10k SE,Av=-1V/V Cout=1000F
%
2 1 0.5
0.2 0.1 0.05
20Hz 15kHz 1kHz
200m 300m 400m 500m 700m 1 2 3 Vo-Output Voltage-Vrms
Vo=1Vrms
0.02 0.01 20
0.02 0.01 100m
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 21
Figure 22
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G1428
Supply Ripple Rejection Ratio vs Frequency
+0 -10 -20 -30 -40 d B -50 -60 -70 -80 -90 -100 20
Supply Ripple Rejection Ratio vs Frequency
+0 -10 -20 -30 -40 d B -50 -60 -70
TT
VDD=5V RL=8 Cb=1F BTL
T
T
T
TT
VDD=5V RL=8 Cb=1F SE
Av=-24V/V
Av=-2V/V
-80 -90 -100 20
50
100
200
5 00 Hz
1k
2k
5k
10k
20 k
50
100
200
5 00 Hz
1k
2k
5k
10k
20 k
Figure 23
Figure 24
Channel Separation
-20 -25 -30 -35 -40 -45 -50 -55 d B -60 -65 -70 -75 -80 -85 -90 -95 -100 20 50 100 200 d B
Channel Separation
+0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100
T
VDD=5V Po=1W RL=8 BTL,Av=-2V/V
VDD=5V Vo=1Vrms RL=10k SE,Av=-1V/V
L TO R
L TO R
R TO L
R TO L
5 00 Hz 1k 2k 5k 10k 20 k
-110 -120 20
50
100
200
5 00 Hz
1k
2k
5k
10k
20 k
Figure 25
Figure 26
Output Noise vs Frequency
5 00u 4 00u 3 00u
Output Power vs Load Resistance
2.5
2 00u
Output Power(W)
VDD=5V RL=4 BTL,Av=-2V/V A-Weighted filter
2 1.5 1 0.5 0 0 10
1 00u V 70u 60u 50u 40u 30u 20u
VDD=5V THD+N=1% BTL Each Channel
10u 20
50
100
200
5 00 Hz
1k
2k
5k
10k
20 k
20
Load Resistance()
30
40
Figure 27
Figure 28
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G1428
Output Power vs Load Resistance
0.7 0.6 Power Dissipation Output Power(W) 0.5 0.4 0.3 0.2 0.1 0 4 8 12 16 20 24 28 32 Load Resistance() VDD=5V THD+N=1% SE Each Channel 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0
Power Dissipation vs Output Power
RL=3
RL=4 VDD=5V BTL Each Channel
RL=8
0.5
1
1.5
2
2.5
Po-Output Power(W)
Figure 29
Figure 30
Power Dissipation vs Output Power
0.35 0.3 Power Dissipation(W) 0.25 0.2
RL=8 RL=4
Recommended PCB Footprint
0.15 0.1
RL=32 VDD=5V SE Each Channel
0.05 0 0
0.2
0.4
0.6
0.8
Po-Output Power(W)
Figure 31
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Pin Description
PIN
1,12,13,24 2 3 4 5
G1428
NAME
GND/HS GAIN0 GAIN1 LOUT+ LLINEIN
I/O
I I O I
FUNCTION
Ground connection for circuitry, directly connected to thermal pad. Bit 0 of gain control Bit 1 of gain control Left channel + output in BTL mode, + output in SE mode. Left channel line input, selected when HP/ LINE pin is held low.
6 7,18 8 9 10 11 14 15 16 17 19 20 21 22 23
LPHIN PVDD RIN LOUTLIN BYPASS PC-BEEP SE/ BTL ROUTHP/ LINE VDD RHPIN ROUT+
SHUTDOWN
I I I O I I I O I
Left channel headphone input, selected when HP/ LINE pin is held high. Power supply for output stages. Common right input for fully differential inputs. AC ground for single-ended inputs. Left channel - output in BTL mode, and high impedance in SE mode. Common left input for fully differential inputs. AC ground for single-ended inputs. Tap to voltage divider for internal mid-supply bias generator. The input for PC-BEEP mode. PC-BEEP is enabled when at least eight continuous > 1-VPP (peak to peak) square waves is input to PC-BEEP pin. Hold low for BTL mode, hold high for SE mode. Right channel - output in BTL mode, high impedance state in SE mode. MUX control input, hold high to select headphone inputs (6,20), hold low to select line inputs (5,23). Analog VDD input supply. This terminal needs to be isolated from PVDD to achieve highest performance. Right channel headphone input, selected when HP/ LINE pin is held high. Right channel + output in BTL mode, positive output in SE mode. Places entire IC in shutdown mode when held low, expect PC-BEEP remains active. Right channel line input, selected when HP/ LINE pin is held low.
I O I I
RLINEIN
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Block Diagram
G1428
RLINEIN RHPIN
Right MUX
RIN PC-Beep
PC-Beep
Depop Circuitry
GAIN0 GAIN1 SE/BTL HP/LINE
Gain/MUX Control
LLINEIN LHPIN
Left MUX
LIN
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+
BYPASS
+ + + _
ROUTPVDD
Power Management
_ _
GND
ROUT+
VDD SHUTDOWN
_ _ _ _
LOUT+
LOUT-
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Application Circuit
G1428
Right Linein Negative Differential Input 1F
23 20
RLINEIN RHPIN
Right MUX
Right Hpin/Linein Positive 1F Differential Input
8 14
RIN PC-Beep BYPASS
PC-Beep
2.2F 2 3 15 17 5 6 Left Hpin Negative 1F Differential Input Left Hpin/Linein Positive Differential Input 1F GAIN0 GAIN1 SE/BTL HP/LINE LLINEIN LHPIN
Left Linein Negative Differential Input 1F
Gain/MUX Control
Left MUX
10
LIN
Application Circuit Using Differential Inputs
Note: 1F ceramic capacitor should be placed as close as possible to the IC to filter the higher-frequency noise.
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11
+ +
11
Depop Circuitry
+ +
+
_
1F PC-BEEP Input Signal
+
ROUT16 VDD 220F 1K PVDD
Power Management
_ _ _ _
1F Right Hpin Negative Differential Input
ROUT+
21
7,18 VDD 19 22 1F 10F Note 100K 4 220F 1K
VDD SHUTDOWN 1,12,13,24 GND
LOUT+
LOUT-
3
0.1F
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Application Circuit (Continued)
G1428
Right Linein Input
1F
23 20
RLINEIN RHPIN
Right MUX
Right Hpin Input
1F
8 14
RIN PC-Beep BYPASS
PC-Beep
2.2F 2 3 15 Left Linein Input 1F 17 5 6 Left Hpin Input 1F GAIN0 GAIN1 SE/BTL HP/LINE LLINEIN LHPIN
Gain/MUX Control
Left MUX
10 1F
LIN
Application Circuit Using Single-Ended Inputs
Note: 1F ceramic capacitor should be placed as close as possible to the IC to filter the higher-frequency noise.
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12
+ +
11
Depop Circuitry
+ +
+
_
1F PC-BEEP Input Signal
+
ROUT16 VDD 220F 1K PVDD
Power Management
_ _ _ _
1F
ROUT+
21
7,18 VDD 19 22 1F 10F Note 100K 4 220F 1K
VDD SHUTDOWN 1,12,13,24 GND
LOUT+
LOUT-
3
0.1F
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Application Information
Gain setting via GAIN0 and GAIN1 inputs
The internal gain setting is determined by two input terminals, GAIN0 and GAIN1. The gains listed in Table 1 are realized by changing the taps on the input resistors inside the amplifier. This will cause the internal input impedance, ZI, to be dependent on the gain setting. Although the real input impedance will shift by 30% due to process variation from part-to-part, the actual gain settings are controlled by the ratios of the resistors and the actual gain distribution from part-topart is quite good. Table 1 GAIN0
0 0 1 1 X
G1428
AV (V/V)
-24 -12 -6 -2 15 30 45 90
Table 2 Zi (Kohm)
Input Capacitor
In the typical application, an input capacitor Ci is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation. In this case ,Ci and the input impedance of the amplifier, Zi, form a high-pass filter with the -3dB determined by the equation: f-3dB= 1/ (2RI Ci) The value of Ci is important to consider as it directly affects the bass performance of the application circuit. For example, if the input resistor is 15k, the input capacitor is 1F, the flat bass response will be down to 10.6Hz. Because the small leakage current of the input capacitors will cause the dc offset voltage at the input to the amplifier that reduces the operation headroom, especially at the high gain applications. The lowleakage tantalum or ceramic capacitors are suggested to be used as the input coupling capacitors. When using the polarized capacitors, it is important to let the positive side connecting to the higher dc level of the application.
GAIN1
0 1 0 1 X
SE/ BTL
0 0 0 0 1
AV (V/V)
-2 -6 -12 -24 -1
Input Resistance
The typical input impedance at each gain setting is given in the Table 2. Each gain setting is achieved by varying the input resistance of the amplifier, which can be over 6 times from its minimum value to the maximum value. As a result, if a single capacitor is used in the input high pass filter, the -3dB or cut-off frequency will be also change over 6 times. To reduce the variation of the cut-off frequency, an additional resistor can be connected from the input pin of the amplifier to the ground, as shown in Figure 1. With the extra resistor, the cut-off frequency can be re-calculated using equation : f-3dB= 1/ 2C(R||RI). Using small external R can reduce the variation of the cut-off frequency. But the side effect is small external R will also let (R||RI) become small, the cut-off frequency will be larger and degraded the bass-band performance. The other side effect is with extra power dissipation through the external resistor R to the ground. So using the external resistor R to flatting the variation of the cut-off frequency, the user must also consider the bass-band performance and the extra power dissipation to choose the accepted external resistor R value.
Power Supply Decoupling
The G1428 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to make sure the output total harmonic distortion (THD) as low as possible. The optimum decoupling is using two capacitors with different types that target different types of noise on the power supply leads. For high frequency transients, spikes, a good low ESR ceramic capacitor works best, typically 0.1F/1F used and placed as close as possible to the G1428 VDD lead. A larger aluminum electrolytic capacitor of 10uF or greater placed near the device power is recommended for filtering low-frequency noise.
Optimizing DEPOP Operation
C Input Signal IN R
Zi
Zf
Circuitry has been implemented in G1428 to minimize the amount of popping heard at power-up and when coming out of shutdown mode. Popping occurs whenever a voltage step is applied to the speaker and making the differential voltage generated at the two ends of the speaker. To avoid the popping heard, the bypass capacitor should be chosen promptly, 1/(CBx170k) 1/(CI*(RI+RF)).
Figure 1
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Where 170k is the output impedance of the mid-rail generator, CB is the mid-rail bypass capacitor, CI is the input coupling capacitor, RI is the input impedance, RF is the gain setting impedance which is on the feedback path. CB is the most important capacitor. Besides it is used to reduce the popping, CB can also determine the rate at which the amplifier starts up during startup or recovery from shutdown mode. De-popping circuitry of G1428 is shown as below Figure 2. The PNP transistor limits the voltage drop across the 120k by slewing the internal node slowly when power is applied. At start-up, the voltage at BYPASS capacitor is 0. The PNP is ON to pull the mid-point of the bias circuit down. So the capacitor sees a lower effective voltage, and thus the charging is slower. This appears as a linear ramp (while the PNP transistor is conducting), followed by the expected exponential ramp of an R-C circuit. For better performance, CB is recommended to be at least 1.5 times of input coupling capacitor CI. For example, if using 1uF input coupling capacitor, 2.2F ceramic or tantalum low-ESR capacitors are recommended to achieve the better THD performance.
VDD 100 k 120 k Bypass 100 k
-3 dB
G1428
Output coupling capacitor G1428 can drive clean, low distortion SE output power with gain -1V/V into headphone loads (generally 16 or 32) as in Figure 3. Please refer to Electrical Characteristics to see the performances. A coupling capacitor is needed to block the dc-offset voltage, allowing pure ac signals into headphone loads. Choosing the coupling capacitor will also determine the -3dB point of the high-pass filter network, as Figure 4.
fC=1/(2RLCC) For example, a 220F capacitor with 32 headphone load would attenuate low frequency performance below 22.6Hz. So the coupling capacitor should be well chosen to achieve the excellent bass performance when in SE mode operation.
VDD
Vo(PP)
CC RL Vo(PP)
Figure 3
fc
Figure 2
Figure 4
Ver: 1.2 Mar 31, 2005
TEL: 886-3-5788833 http://www.gmt.com.tw
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Global Mixed-mode Technology Inc.
Bridged-Tied Load Mode Operation G1428 has two linear amplifiers to drive both ends of the speaker load in Bridged-Tied Load (BTL) mode operation. Figure 5 shows the BTL configuration. The differential driving to the speaker load means that when one side is slewing up, the other side is slewing down, and vice versa. This configuration in effect will double the voltage swing on the load as compared to a ground reference load. In BTL mode, the peak-to-peak voltage VO(PP) on the load will be two times than a ground reference configuration. The voltage on the load is doubled, this will also yield 4 times output power on the load at the same power supply rail and loading. Another benefit of using differential driving configuration is that BTL operation cancels the dc offsets, which eliminates the dc coupling capacitor that is needed to cancelled dc offsets in the ground reference configuration. Low-frequency performance is then limited only by the input network and speaker responses. Cost and PCB space can be minimized by eliminating the dc coupling capacitors.
G1428
Shutdown mode When the normal operation, the SHUTDOWN pin should be held high. Pulling SHUTDOWN low will mute the outputs and deactivate almost circuits except PC-BEEP monitoring block. At this moment, the current of this device will be reduced to about 160uA to save the battery energy. The SHUTDOWN pin should never be left unconnected during the normal applications. INPUT * HP/ LINE SE/ BTL SHUTDOWN
X Low Low High High X Low High Low High Low High High High High
AMPLIFIER STATE
INPUT OUTPUT
X Line Line headphone headphone Mute BTL SE BTL SE
* Inputs should never be left unconnected X= do not care
VDD
Vo(PP) RL 2xVo(PP) -Vo(PP)
VDD
PC-BEEP Operation The PC-BEEP input allows a system beep to be sent directly from a computer through the amplifier to the speakers with a few external components. It is activated automatically by detecting the PC-BEEP input. The preferred input signal is a square wave or pulse train with an amplitude of 1-VPP or greater. To be accurately detected, the signal must be with at least 1 -VPP amplitude, 8 continuous rising edges, rise and fall times less than 0.1us. When the signal is no longer detected, the amplifier will return its previous operating mode and volume setting.
When the PC-BEEP mode is activated, both the LINEIN and HPIN are deselected and the outputs will be driven in BTL mode with the signal from PC-BEEP. The gain setting will be also fixed at 0.3V/V, independent of the volume setting. If the device is in the SHUTDOWN mode, activating PC-BEEP will take the device out of shutdown mode and output the PC-BEEP input signal until the PC-BEEP signal no longer detected. And then the device will return the shutdown mode when no PC-BEEP signal is detected. The PC-BEEP input can also be dc-coupled to save the coupling capacitor. This pin is set at mid-rail normally when no signal is present. If AC-coupling is desired, the value of the coupling capacitor should be chosen to satisfy the equation : CPCB 1/( 2fPCB*150K) CPCB is the PC-BEEP AC-coupling capacitor. fPCB is the frequency of applied PC-BEEP input signal.
Figure 5
Input MUX And SE/BTL Operation The G1428 allows two different input sources applied to the audio amplifiers, which can be independent to the SE/BTL setting. When HP/LINE is held high, the headphone inputs are active. When the HP/LINE is held low, the line inputs are selected. When SE/BTL is held low, all four internal audio amplifiers are activated to drive the stereo speakers. When SE/BTL is held high, two amplifiers are activated to drive the stereo headphones. The other two amplifiers are disable and keeping the outputs high impedance.
Ver: 1.2 Mar 31, 2005
TEL: 886-3-5788833 http://www.gmt.com.tw
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Global Mixed-mode Technology Inc.
Package Information
D 24
C
G1428
L
1.88
3.85
1.88
2.8
E1 E
0.71
1
Note 5
A2 A1 e b
A
Note: 1. Package body sizes exclude mold flash protrusions or gate burrs 2. Tolerance 0.1mm unless otherwise specified 3. Coplanarity : 0.1mm 4. Controlling dimension is millimeter. Converted inch dimensions are not necessarily exact. 5. Die pad exposure size is according to lead frame design. 6. Follow JEDEC MO-153
SYMBOL
A A1 A2 b C D E E1 e L y
MIN.
----0.00 0.80 0.19 0.09 7.70 6.20 4.30 ----0.45 ----0
DIMENSION IN MM NOM.
--------1.00 --------7.80 6.40 4.40 0.65 0.60 ---------
MAX.
1.15 0.10 1.05 0.30 0.20 7.90 6.60 4.50 ----0.75 0.10 8
MIN.
----0.000 0.031 0.007 0.004 0.303 0.244 0.169 ----0.018 ----0
DIMENSION IN INCH NOM.
--------0.039 --------0.307 0.252 0.173 0.026 0.024 ---------
MAX.
0.045 0.004 0.041 0.012 0.008 0.311 2.260 0.177 ----0.030 0.004 8
Taping Specification
PACKAGE
TSSOP-24 (FD)
Q'TY/BY REEL
2,500 ea
F e e d D ir e c tio n T y p ic a l T S S O P P a c k a g e O r ie n ta tio n
GMT Inc. does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and GMT Inc. reserves the right at any time without notice to change said circuitry and specifications.
Ver: 1.2 Mar 31, 2005
TEL: 886-3-5788833 http://www.gmt.com.tw
16

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